A processor pipeline is composed of many stages where each stage performs a specific function related to an instruction. Each stage is referred to as a pipe stage or pipe segment. The stages are connected together to form the pipeline. Instructions enter at one end of the pipeline and exit at the other end. The instructions flow sequentially in a stream through the pipeline stages. The stages are arranged so that several stages can be simultaneously processing several instructions. Simultaneously processing multiple instructions at different pipeline stages allows the processor to process instructions faster than processing one instruction at a time, thus improving the execution speed of the processor.
Within the processor, there may be multiple pipelines processing instructions. The individual pipelines may perform unique processor functions. For example, a processor may have one pipeline for executing load/store instructions and another pipeline for executing integer or logic based instructions. By separating the pipelines based on functionality of the instruction, the processor may more efficiently utilize its resources when executing the instructions.
When the processor processes instructions, information necessary to execute the instruction is gathered. The information may be related to each operand in the instruction. Within the processor, the amount of information that may be simultaneously gathered for each instruction may be limited by the number of ports within the processor's register file. The processor's register file may consist of a large array that is read and write accessible. The number of read ports that the processor supports may be limited by the available hardware space within the processor as well as the additional power necessary for each read port. The processor utilizes each read port to retrieve information related to each operand in the instruction.
As more complex instructions are added to the processor's instruction set, additional read ports may be required in order to simultaneously retrieve information for all of the operands in the instructions when the instruction is executing. Commonly, newer instructions may have more operands than read ports. If the processor does not have enough read ports, the instruction may need additional processor cycles to execute. In turn, the processor's efficiency may be impacted.
One type of instruction that may be affected by an execution delay related to the restriction of the number of read ports is a conditional instruction. Conditional instructions commonly consist of a conditional part, and a non-conditional part such as a logical function, arithmetic function, or the like. Due to the lack of read ports, a conditional instruction having more operands than read ports may need multiple processor cycles to execute.